Flex Logix EFLX4K IO eFPGA Core Enables Very Wide Bus Connections for Networking Applications
Poster: SySAdmin
Posted on June 26, 2018 at 7:07:01 AM
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style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th> </tr></tbody></table><table class="row sub-header"style="background:#00837E;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="16px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;hyphens:auto;line-height:16px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <h4 class="text-center" style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:18px;font-weight:400;hyphens:none;line-height:22px;margin:0;margin-bottom:10px;padding:0;text-align:center;text-transform:uppercase;word-break:none;word-wrap:normal">News From Flex Logix Technologies, Inc.</h4><h5 class="text-center" style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:14px;font-weight:500;hyphens:none;line-height:18px;margin:0;margin-bottom:0;padding:0;text-align:center;word-break:none;word-wrap:normal">Transmitted by PR Newswire for Journalists on <span class="prevent-break" style="display:inline-block">June 26, 2018 07:00 AM EST </span></h5></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row header" style="background:#e5f2f3;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:0;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <h1 style="Margin:0;Margin-bottom:10px;color:#4D4E53;font-family:Montserrat,Arial,sans-serif;font-size:20px;font-weight:500;line-height:28px;margin:0;margin-bottom:0;padding:0;text-align:left;word-wrap:normal">Flex Logix EFLX4K IO eFPGA Core Enables Very Wide Bus Connections for Networking Applications</h1> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> </th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th> </tr></tbody></table> <table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table><p><span class="xn-location">MOUNTAIN VIEW, Calif.</span>, <span class="xn-chron">June 26, 2018</span> /PRNewswire/ -- <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj0Co-2Bwt-2Bmo8dBZPQCqHnm6HTut8SU3rqXauecAzzSWZh_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75L42mUDz5AIEpRtdL2ofiAmXGGYokGHHEQzdy6wkxBwD5NPW9Kv-2F3CIRYKjuk0mQ0759nL-2BxSWLOnFZR3TEG-2BarvhfBjFTuB-2FJo1P3cW9s-2FUxiKtJ5oFPQbiKzGkufK3stgNBK1yMBh01D5Z-2BVEzb55oBBFZ2z6QYasssdCHb-2BxO-2BJvSRAnldTk6C00cH89eRZSe-2B0h6JSxrNb-2Fb0V7IQD2uXtbQykftM57IlVeX4vcJCiIo-2F7MowvDTLQKZmKZRBmSKCBpAzQdKvF95BUaKAJA-3D-3D" rel="nofollow" target="_blank">Flex Logix<span>®</span> Technologies, Inc</a>. the leading supplier of embedded FPGA (eFPGA) IP, architecture and software, announced today a new member of the EFLX<span>®</span><span class="xn-money">4K</span> eFPGA Core Family: the EFLX4K IO eFPGA core. This new core is designed for networking and applications with many heterogeneous processors where customers need to connect very wide buses with relatively small eFPGAs. </p>
<p>"Customers can achieve significant performance advantages when they can connect very wide buses as needed in their designs," said <span class="xn-person">Geoff Tate</span>, CEO and cofounder of Flex Logix. "While traditional FPGA lacked this flexibility, eFPGA can be easily optimized for various bus sizes, which is critical in networking applications that need as much performance as possible."</p><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><center data-parsed="" style="min-width:510px;width:100%"><img src="https://mma.prnewswire.com/media/394413/Flex_Logix_Technologies_Logo.jpg" alt="" align="center" class="float-center" style="-ms-interpolation-mode:bicubic;Margin:0 auto;clear:both;display:block;float:none;margin:0 auto;max-width:100%;outline:0;text-align:center;text-decoration:none;width:auto"></center></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left">
<p>The EFLX4K IO eFPGA core is a derivative of the EFLX4K Logic core optimized for very wide buses. It is available now for implementation on any new process node in about 6-8 months (less where the EFLX4K Logic eFPGA is already implemented). The dimensions of the EFLX4K IO are identical to the EFLX4K Logic and DSP cores to deliver the most flexibility in creating an arrayable solution from a single array (~4K LUT4 equivalents) to at least a 7x7 array (over ~200K LUT4 equivalents). The interconnect network is the same, silicon proven network in the current EFLX4K cores: what changes is that some of the programmable logic is replaced with I/O.</p>
<p>The EFLX4K IO eFPGA core has 1640 inputs and 1640 outputs. This compares to 632 inputs and 632 outputs for the EFLX4K Logic core. The extra inputs and outputs are asymmetrically added all on one side since in typical networking applications the number of input signals are much more than the number of output signals. With the EFLX4K IO eFPGA core, a 1024 bit wide bus can be wired into one side! Wider bus inputs can be handled using multiple EFLX4K IO cores in an array as needed.</p>
<p>The EFLX4K IO can be intermixed in arrays of at least 7x7 with the EFLX4K Logic and DSP cores.</p>
<p>Learn more about the EFLX4K IO from our technologists at DAC, <span class="xn-chron">Monday June 25 - Wednesday June 27</span> at Flex Logix's booth #2318. Or email us at <a href="mailto:info@flex-logix.com" rel="nofollow" target="_blank">info@flex-logix.com</a> </p>
<p>About Flex Logix <br>Flex Logix, founded in <span class="xn-chron">March 2014</span>, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores, architecture and software. eFPGA can accelerate key workloads 10-100x faster than processors, enable chips to adapt to changing algorithms, protocols, etc and to customize mask sets to meet the needs of multiple customers or market segments. Flex Logix has unique, patented technology for implementing eFPGA: XFLX hierarchical interconnect with twice the density of traditional FPGA mesh interconnect, ArrayLinx interconnect enabling arrays of various sizes and features to be constructed in days from silicon proven GDS blocks, and RAMLinx for integrating any kind of RAM the customer needs. Flex Logix's co-founders Cheng Wang and <span class="xn-person">Dejan Markovic</span> were recognized with the prestigious Outstanding Paper Award by ISSCC for their paper on XFLX technology. Flex Logix's other co-founder <span class="xn-person">Geoff Tate</span> was the founding CEO of Rambus, which pioneered the Semiconductor IP business model, taking the company from 4 employees to a <span class="xn-money">$2 billion</span> market Capitalization. The company's technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers' hardware. Flex Logix has secured approximately <span class="xn-money">$13 million</span> of venture backed capital, is headquartered in <span class="xn-location">Mountain View, California</span> and has sales rep offices in <span class="xn-location">China</span>, <span class="xn-location">Europe</span>, <span class="xn-location">Israel</span>, <span class="xn-location">Japan</span>, <span class="xn-location">Taiwan</span>. More information can be obtained at <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj0Co-2Bwt-2Bmo8dBZPQCqHnm6HTut8SU3rqXauecAzzSWZh_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75L42mUDz5AIEpRtdL2ofiAmXGGYokGHHEQzdy6wkxBwD5NPW9Kv-2F3CIRYKjuk0mQ0759nL-2BxSWLOnFZR3TEG-2BarvhfBjFTuB-2FJo1P3cW9s-2FUxiKtJ5oFPQbiKzGkufK3sK8-2FwnNPEc9wZfPvP7i5Bw1OXrRqFm9t4al5sqoVcMMjm2Oz9Of2XLd-2FIMb7tzRF2nFxcms16Aj3Omufi2Fii4jB4r1Nycml-2BPdOK2jOj3l-2FTlfp1e62cZLdZc4rxMJ3pFutVY71OEbmICDblIxP6Rg-3D-3D" rel="nofollow" target="_blank">http://www.flex-logix.com</a> or follow on Twitter at @efpga.</p>
<p>MEDIA CONTACTS<br><span class="xn-person">Kelly Karr</span><br>Tanis Communications<br><a href="mailto:kelly.karr@taniscomm.com" rel="nofollow" target="_blank">kelly.karr@taniscomm.com</a><br>+408-718-9350</p>
<p>Copyright 2018. All rights reserved. Flex Logix and EFLX are registered trademarks of Flex Logix, Inc.</p>
<p> </p>
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<p>"Customers can achieve significant performance advantages when they can connect very wide buses as needed in their designs," said <span class="xn-person">Geoff Tate</span>, CEO and cofounder of Flex Logix. "While traditional FPGA lacked this flexibility, eFPGA can be easily optimized for various bus sizes, which is critical in networking applications that need as much performance as possible."</p><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><center data-parsed="" style="min-width:510px;width:100%"><img src="https://mma.prnewswire.com/media/394413/Flex_Logix_Technologies_Logo.jpg" alt="" align="center" class="float-center" style="-ms-interpolation-mode:bicubic;Margin:0 auto;clear:both;display:block;float:none;margin:0 auto;max-width:100%;outline:0;text-align:center;text-decoration:none;width:auto"></center></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left">
<p>The EFLX4K IO eFPGA core is a derivative of the EFLX4K Logic core optimized for very wide buses. It is available now for implementation on any new process node in about 6-8 months (less where the EFLX4K Logic eFPGA is already implemented). The dimensions of the EFLX4K IO are identical to the EFLX4K Logic and DSP cores to deliver the most flexibility in creating an arrayable solution from a single array (~4K LUT4 equivalents) to at least a 7x7 array (over ~200K LUT4 equivalents). The interconnect network is the same, silicon proven network in the current EFLX4K cores: what changes is that some of the programmable logic is replaced with I/O.</p>
<p>The EFLX4K IO eFPGA core has 1640 inputs and 1640 outputs. This compares to 632 inputs and 632 outputs for the EFLX4K Logic core. The extra inputs and outputs are asymmetrically added all on one side since in typical networking applications the number of input signals are much more than the number of output signals. With the EFLX4K IO eFPGA core, a 1024 bit wide bus can be wired into one side! Wider bus inputs can be handled using multiple EFLX4K IO cores in an array as needed.</p>
<p>The EFLX4K IO can be intermixed in arrays of at least 7x7 with the EFLX4K Logic and DSP cores.</p>
<p>Learn more about the EFLX4K IO from our technologists at DAC, <span class="xn-chron">Monday June 25 - Wednesday June 27</span> at Flex Logix's booth #2318. Or email us at <a href="mailto:info@flex-logix.com" rel="nofollow" target="_blank">info@flex-logix.com</a> </p>
<p>About Flex Logix <br>Flex Logix, founded in <span class="xn-chron">March 2014</span>, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores, architecture and software. eFPGA can accelerate key workloads 10-100x faster than processors, enable chips to adapt to changing algorithms, protocols, etc and to customize mask sets to meet the needs of multiple customers or market segments. Flex Logix has unique, patented technology for implementing eFPGA: XFLX hierarchical interconnect with twice the density of traditional FPGA mesh interconnect, ArrayLinx interconnect enabling arrays of various sizes and features to be constructed in days from silicon proven GDS blocks, and RAMLinx for integrating any kind of RAM the customer needs. Flex Logix's co-founders Cheng Wang and <span class="xn-person">Dejan Markovic</span> were recognized with the prestigious Outstanding Paper Award by ISSCC for their paper on XFLX technology. Flex Logix's other co-founder <span class="xn-person">Geoff Tate</span> was the founding CEO of Rambus, which pioneered the Semiconductor IP business model, taking the company from 4 employees to a <span class="xn-money">$2 billion</span> market Capitalization. The company's technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers' hardware. Flex Logix has secured approximately <span class="xn-money">$13 million</span> of venture backed capital, is headquartered in <span class="xn-location">Mountain View, California</span> and has sales rep offices in <span class="xn-location">China</span>, <span class="xn-location">Europe</span>, <span class="xn-location">Israel</span>, <span class="xn-location">Japan</span>, <span class="xn-location">Taiwan</span>. More information can be obtained at <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj0Co-2Bwt-2Bmo8dBZPQCqHnm6HTut8SU3rqXauecAzzSWZh_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75L42mUDz5AIEpRtdL2ofiAmXGGYokGHHEQzdy6wkxBwD5NPW9Kv-2F3CIRYKjuk0mQ0759nL-2BxSWLOnFZR3TEG-2BarvhfBjFTuB-2FJo1P3cW9s-2FUxiKtJ5oFPQbiKzGkufK3sK8-2FwnNPEc9wZfPvP7i5Bw1OXrRqFm9t4al5sqoVcMMjm2Oz9Of2XLd-2FIMb7tzRF2nFxcms16Aj3Omufi2Fii4jB4r1Nycml-2BPdOK2jOj3l-2FTlfp1e62cZLdZc4rxMJ3pFutVY71OEbmICDblIxP6Rg-3D-3D" rel="nofollow" target="_blank">http://www.flex-logix.com</a> or follow on Twitter at @efpga.</p>
<p>MEDIA CONTACTS<br><span class="xn-person">Kelly Karr</span><br>Tanis Communications<br><a href="mailto:kelly.karr@taniscomm.com" rel="nofollow" target="_blank">kelly.karr@taniscomm.com</a><br>+408-718-9350</p>
<p>Copyright 2018. All rights reserved. Flex Logix and EFLX are registered trademarks of Flex Logix, Inc.</p>
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